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flakes/packages/linux-lava/si-manual-clocking.patch
LavaDesu 1e4d6d2177
kernel: bump to 5.14.1
2021-09-08 00:11:17 +07:00

217 lines
7.4 KiB
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From 8676738da851887056cb4461f70848ddeef35263 Mon Sep 17 00:00:00 2001
From: LavaDesu <me@lava.moe>
Date: Tue, 7 Sep 2021 09:32:22 +0700
Subject: [PATCH] Lava's amdgpu patches
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h | 6 ++
drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c | 2 +-
drivers/gpu/drm/amd/pm/amdgpu_pm.c | 112 +++++++++++++++++++-
drivers/gpu/drm/amd/pm/powerplay/si_dpm.c | 17 +++
4 files changed, 131 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 8ac6eb9f1fd..33ccd30800a 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -212,6 +212,12 @@ extern int amdgpu_mes;
extern int amdgpu_noretry;
extern int amdgpu_force_asic_type;
extern int amdgpu_smartshift_bias;
+
+extern __u32 amdgpu_force_mclk;
+extern __u32 amdgpu_force_sclk;
+extern __u32 amdgpu_force_vddc;
+extern __u32 amdgpu_force_vddci;
+
#ifdef CONFIG_HSA_AMD
extern int sched_policy;
extern bool debug_evictions;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c
index a9475b20751..5f558684bd1 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c
@@ -100,7 +100,7 @@ static int amdgpu_dma_buf_attach(struct dma_buf *dmabuf,
struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
int r;
- if (pci_p2pdma_distance_many(adev->pdev, &attach->dev, 1, true) < 0)
+ if (pci_p2pdma_distance_many(adev->pdev, &attach->dev, 1, amdgpu_dpm == 1) < 0)
attach->peer2peer = false;
if (attach->dev->driver == adev->dev->driver)
diff --git a/drivers/gpu/drm/amd/pm/amdgpu_pm.c b/drivers/gpu/drm/amd/pm/amdgpu_pm.c
index 769f58d5ae1..614a14bde84 100644
--- a/drivers/gpu/drm/amd/pm/amdgpu_pm.c
+++ b/drivers/gpu/drm/amd/pm/amdgpu_pm.c
@@ -36,6 +36,11 @@
#include <asm/processor.h>
#include "hwmgr.h"
+__u32 amdgpu_force_mclk = 0;
+__u32 amdgpu_force_sclk = 0;
+__u32 amdgpu_force_vddc = 0;
+__u32 amdgpu_force_vddci = 0;
+
static const struct cg_flag_name clocks[] = {
{AMD_CG_SUPPORT_GFX_FGCG, "Graphics Fine Grain Clock Gating"},
{AMD_CG_SUPPORT_GFX_MGCG, "Graphics Medium Grain Clock Gating"},
@@ -2002,6 +2007,94 @@ static int ss_bias_attr_update(struct amdgpu_device *adev, struct amdgpu_device_
return 0;
}
+/*
+ * DOC: pp_override_mclk
+ *
+ * It's like pp_od_clk_voltage but worse and can potentially destroy your gpu idk
+ */
+static ssize_t amdgpu_get_pp_override_mclk(struct device *dev,
+ struct device_attribute *attr,
+ char *buf)
+{
+ DRM_INFO("[Lava] Read pp_override_mclk\n");
+ return sprintf(buf, "%u", amdgpu_force_mclk);
+}
+static ssize_t amdgpu_set_pp_override_mclk(struct device *dev,
+ struct device_attribute *attr,
+ const char *buf,
+ size_t count)
+{
+ sscanf(buf, "%u", &amdgpu_force_mclk);
+ DRM_INFO("[Lava] Write pp_override_mclk, %u\n", amdgpu_force_mclk);
+ return count;
+}
+
+/**
+ * DOC: pp_override_sclk
+ *
+ * pp_override_mclk but sclk
+ */
+static ssize_t amdgpu_get_pp_override_sclk(struct device *dev,
+ struct device_attribute *attr,
+ char *buf)
+{
+ DRM_INFO("[Lava] Read pp_override_sclk\n");
+ return sprintf(buf, "%u", amdgpu_force_sclk);
+}
+static ssize_t amdgpu_set_pp_override_sclk(struct device *dev,
+ struct device_attribute *attr,
+ const char *buf,
+ size_t count)
+{
+ sscanf(buf, "%u", &amdgpu_force_sclk);
+ DRM_INFO("[Lava] Write pp_override_sclk, %u\n", amdgpu_force_sclk);
+ return count;
+}
+
+/**
+ * DOC: pp_override_vddc
+ *
+ * pp_override_mclk but vddc
+ */
+static ssize_t amdgpu_get_pp_override_vddc(struct device *dev,
+ struct device_attribute *attr,
+ char *buf)
+{
+ DRM_INFO("[Lava] Read pp_override_vddc\n");
+ return sprintf(buf, "%u", amdgpu_force_vddc);
+}
+static ssize_t amdgpu_set_pp_override_vddc(struct device *dev,
+ struct device_attribute *attr,
+ const char *buf,
+ size_t count)
+{
+ sscanf(buf, "%u", &amdgpu_force_vddc);
+ DRM_INFO("[Lava] Write pp_override_vddc, %u\n", amdgpu_force_vddc);
+ return count;
+}
+
+/**
+ * DOC: pp_override_vddci
+ *
+ * pp_override_mclk but vddci
+ */
+static ssize_t amdgpu_get_pp_override_vddci(struct device *dev,
+ struct device_attribute *attr,
+ char *buf)
+{
+ DRM_INFO("[Lava] Read pp_override_vddci\n");
+ return sprintf(buf, "%u", amdgpu_force_vddci);
+}
+static ssize_t amdgpu_set_pp_override_vddci(struct device *dev,
+ struct device_attribute *attr,
+ const char *buf,
+ size_t count)
+{
+ sscanf(buf, "%u", &amdgpu_force_vddci);
+ DRM_INFO("[Lava] Write pp_override_vddci, %u\n", amdgpu_force_vddci);
+ return count;
+}
+
static struct amdgpu_device_attr amdgpu_device_attrs[] = {
AMDGPU_DEVICE_ATTR_RW(power_dpm_state, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
AMDGPU_DEVICE_ATTR_RW(power_dpm_force_performance_level, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
@@ -2034,6 +2127,11 @@ static struct amdgpu_device_attr amdgpu_device_attrs[] = {
.attr_update = ss_power_attr_update),
AMDGPU_DEVICE_ATTR_RW(smartshift_bias, ATTR_FLAG_BASIC,
.attr_update = ss_bias_attr_update),
+
+ AMDGPU_DEVICE_ATTR_RW(pp_override_mclk, ATTR_FLAG_BASIC),
+ AMDGPU_DEVICE_ATTR_RW(pp_override_sclk, ATTR_FLAG_BASIC),
+ AMDGPU_DEVICE_ATTR_RW(pp_override_vddc, ATTR_FLAG_BASIC),
+ AMDGPU_DEVICE_ATTR_RW(pp_override_vddci, ATTR_FLAG_BASIC),
};
static int default_attr_update(struct amdgpu_device *adev, struct amdgpu_device_attr *attr,
@@ -2063,11 +2161,15 @@ static int default_attr_update(struct amdgpu_device *adev, struct amdgpu_device_
if (asic_type < CHIP_VEGA20)
*states = ATTR_STATE_UNSUPPORTED;
} else if (DEVICE_ATTR_IS(pp_od_clk_voltage)) {
- *states = ATTR_STATE_UNSUPPORTED;
- if ((is_support_sw_smu(adev) && adev->smu.od_enabled) ||
- (is_support_sw_smu(adev) && adev->smu.is_apu) ||
- (!is_support_sw_smu(adev) && hwmgr->od_enabled))
- *states = ATTR_STATE_SUPPORTED;
+ *states = ATTR_STATE_SUPPORTED;
+ } else if (DEVICE_ATTR_IS(pp_override_mclk)) {
+ *states = ATTR_STATE_SUPPORTED;
+ } else if (DEVICE_ATTR_IS(pp_override_sclk)) {
+ *states = ATTR_STATE_SUPPORTED;
+ } else if (DEVICE_ATTR_IS(pp_override_vddc)) {
+ *states = ATTR_STATE_SUPPORTED;
+ } else if (DEVICE_ATTR_IS(pp_override_vddci)) {
+ *states = ATTR_STATE_SUPPORTED;
} else if (DEVICE_ATTR_IS(mem_busy_percent)) {
if (adev->flags & AMD_IS_APU || asic_type == CHIP_VEGA10)
*states = ATTR_STATE_UNSUPPORTED;
diff --git a/drivers/gpu/drm/amd/pm/powerplay/si_dpm.c b/drivers/gpu/drm/amd/pm/powerplay/si_dpm.c
index 15c0b8af376..31e520d5e21 100644
--- a/drivers/gpu/drm/amd/pm/powerplay/si_dpm.c
+++ b/drivers/gpu/drm/amd/pm/powerplay/si_dpm.c
@@ -3492,6 +3492,23 @@ static void si_apply_state_adjust_rules(struct amdgpu_device *adev,
&max_mclk_vddc);
for (i = 0; i < ps->performance_level_count; i++) {
+ if (amdgpu_force_mclk) {
+ if (ps->performance_levels[i].mclk > amdgpu_force_mclk)
+ ps->performance_levels[i].mclk = amdgpu_force_mclk;
+ }
+ if (amdgpu_force_sclk) {
+ if (ps->performance_levels[i].sclk > amdgpu_force_sclk)
+ ps->performance_levels[i].sclk = amdgpu_force_sclk;
+ }
+ if (amdgpu_force_vddc) {
+ if (ps->performance_levels[i].vddc > amdgpu_force_vddc)
+ ps->performance_levels[i].vddc = amdgpu_force_vddc;
+ }
+ if (amdgpu_force_vddci) {
+ if (ps->performance_levels[i].vddci > amdgpu_force_vddci)
+ ps->performance_levels[i].vddci = amdgpu_force_vddci;
+ }
+
if (max_sclk_vddc) {
if (ps->performance_levels[i].sclk > max_sclk_vddc)
ps->performance_levels[i].sclk = max_sclk_vddc;
--
2.32.0
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