From 0120e137d9c3aebcb9ac7bd319216a92fbed7499 Mon Sep 17 00:00:00 2001 From: LavaDesu Date: Mon, 3 Oct 2022 22:55:47 +0700 Subject: [PATCH] Lava's amdgpu patches --- drivers/gpu/drm/amd/amdgpu/amdgpu.h | 4 + drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c | 2 +- drivers/gpu/drm/amd/pm/amdgpu_pm.c | 106 ++++++++++++++++++++ drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c | 17 ++++ 4 files changed, 128 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h index d597e2656c4..6eec6b36c52 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h @@ -215,6 +215,10 @@ extern int amdgpu_noretry; extern int amdgpu_force_asic_type; extern int amdgpu_smartshift_bias; extern int amdgpu_use_xgmi_p2p; +extern uint amdgpu_force_mclk; +extern uint amdgpu_force_sclk; +extern uint amdgpu_force_vddc; +extern uint amdgpu_force_vddci; #ifdef CONFIG_HSA_AMD extern int sched_policy; extern bool debug_evictions; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c index 782cbca3753..8cb600cb3b4 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c @@ -58,7 +58,7 @@ static int amdgpu_dma_buf_attach(struct dma_buf *dmabuf, struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); int r; - if (pci_p2pdma_distance_many(adev->pdev, &attach->dev, 1, true) < 0) + if (pci_p2pdma_distance_many(adev->pdev, &attach->dev, 1, amdgpu_dpm == 1) < 0) attach->peer2peer = false; r = pm_runtime_get_sync(adev_to_drm(adev)->dev); diff --git a/drivers/gpu/drm/amd/pm/amdgpu_pm.c b/drivers/gpu/drm/amd/pm/amdgpu_pm.c index 5e318b3f6c0..8da0b91d3ad 100644 --- a/drivers/gpu/drm/amd/pm/amdgpu_pm.c +++ b/drivers/gpu/drm/amd/pm/amdgpu_pm.c @@ -35,6 +35,11 @@ #include #include +__u32 amdgpu_force_mclk = 0; +__u32 amdgpu_force_sclk = 0; +__u32 amdgpu_force_vddc = 0; +__u32 amdgpu_force_vddci = 0; + static const struct cg_flag_name clocks[] = { {AMD_CG_SUPPORT_GFX_FGCG, "Graphics Fine Grain Clock Gating"}, {AMD_CG_SUPPORT_GFX_MGCG, "Graphics Medium Grain Clock Gating"}, @@ -1912,6 +1917,94 @@ static int ss_bias_attr_update(struct amdgpu_device *adev, struct amdgpu_device_ return 0; } +/* + * DOC: pp_override_mclk + * + * It's like pp_od_clk_voltage but worse and can potentially destroy your gpu idk + */ +static ssize_t amdgpu_get_pp_override_mclk(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + DRM_INFO("[Lava] Read pp_override_mclk\n"); + return sprintf(buf, "%u", amdgpu_force_mclk); +} +static ssize_t amdgpu_set_pp_override_mclk(struct device *dev, + struct device_attribute *attr, + const char *buf, + size_t count) +{ + sscanf(buf, "%u", &amdgpu_force_mclk); + DRM_INFO("[Lava] Write pp_override_mclk, %u\n", amdgpu_force_mclk); + return count; +} + +/** + * DOC: pp_override_sclk + * + * pp_override_mclk but sclk + */ +static ssize_t amdgpu_get_pp_override_sclk(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + DRM_INFO("[Lava] Read pp_override_sclk\n"); + return sprintf(buf, "%u", amdgpu_force_sclk); +} +static ssize_t amdgpu_set_pp_override_sclk(struct device *dev, + struct device_attribute *attr, + const char *buf, + size_t count) +{ + sscanf(buf, "%u", &amdgpu_force_sclk); + DRM_INFO("[Lava] Write pp_override_sclk, %u\n", amdgpu_force_sclk); + return count; +} + +/** + * DOC: pp_override_vddc + * + * pp_override_mclk but vddc + */ +static ssize_t amdgpu_get_pp_override_vddc(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + DRM_INFO("[Lava] Read pp_override_vddc\n"); + return sprintf(buf, "%u", amdgpu_force_vddc); +} +static ssize_t amdgpu_set_pp_override_vddc(struct device *dev, + struct device_attribute *attr, + const char *buf, + size_t count) +{ + sscanf(buf, "%u", &amdgpu_force_vddc); + DRM_INFO("[Lava] Write pp_override_vddc, %u\n", amdgpu_force_vddc); + return count; +} + +/** + * DOC: pp_override_vddci + * + * pp_override_mclk but vddci + */ +static ssize_t amdgpu_get_pp_override_vddci(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + DRM_INFO("[Lava] Read pp_override_vddci\n"); + return sprintf(buf, "%u", amdgpu_force_vddci); +} +static ssize_t amdgpu_set_pp_override_vddci(struct device *dev, + struct device_attribute *attr, + const char *buf, + size_t count) +{ + sscanf(buf, "%u", &amdgpu_force_vddci); + DRM_INFO("[Lava] Write pp_override_vddci, %u\n", amdgpu_force_vddci); + return count; +} + static struct amdgpu_device_attr amdgpu_device_attrs[] = { AMDGPU_DEVICE_ATTR_RW(power_dpm_state, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF), AMDGPU_DEVICE_ATTR_RW(power_dpm_force_performance_level, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF), @@ -1944,6 +2037,11 @@ static struct amdgpu_device_attr amdgpu_device_attrs[] = { .attr_update = ss_power_attr_update), AMDGPU_DEVICE_ATTR_RW(smartshift_bias, ATTR_FLAG_BASIC, .attr_update = ss_bias_attr_update), + + AMDGPU_DEVICE_ATTR_RW(pp_override_mclk, ATTR_FLAG_BASIC), + AMDGPU_DEVICE_ATTR_RW(pp_override_sclk, ATTR_FLAG_BASIC), + AMDGPU_DEVICE_ATTR_RW(pp_override_vddc, ATTR_FLAG_BASIC), + AMDGPU_DEVICE_ATTR_RW(pp_override_vddci, ATTR_FLAG_BASIC), }; static int default_attr_update(struct amdgpu_device *adev, struct amdgpu_device_attr *attr, @@ -1976,6 +2074,14 @@ static int default_attr_update(struct amdgpu_device *adev, struct amdgpu_device_ *states = ATTR_STATE_UNSUPPORTED; if (amdgpu_dpm_is_overdrive_supported(adev)) *states = ATTR_STATE_SUPPORTED; + } else if (DEVICE_ATTR_IS(pp_override_mclk)) { + *states = ATTR_STATE_SUPPORTED; + } else if (DEVICE_ATTR_IS(pp_override_sclk)) { + *states = ATTR_STATE_SUPPORTED; + } else if (DEVICE_ATTR_IS(pp_override_vddc)) { + *states = ATTR_STATE_SUPPORTED; + } else if (DEVICE_ATTR_IS(pp_override_vddci)) { + *states = ATTR_STATE_SUPPORTED; } else if (DEVICE_ATTR_IS(mem_busy_percent)) { if (adev->flags & AMD_IS_APU || gc_ver == IP_VERSION(9, 0, 1)) *states = ATTR_STATE_UNSUPPORTED; diff --git a/drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c b/drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c index 49c398ec0aa..1f3f8a210e7 100644 --- a/drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c +++ b/drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c @@ -3507,6 +3507,23 @@ static void si_apply_state_adjust_rules(struct amdgpu_device *adev, &max_mclk_vddc); for (i = 0; i < ps->performance_level_count; i++) { + if (amdgpu_force_mclk) { + if (ps->performance_levels[i].mclk > amdgpu_force_mclk) + ps->performance_levels[i].mclk = amdgpu_force_mclk; + } + if (amdgpu_force_sclk) { + if (ps->performance_levels[i].sclk > amdgpu_force_sclk) + ps->performance_levels[i].sclk = amdgpu_force_sclk; + } + if (amdgpu_force_vddc) { + if (ps->performance_levels[i].vddc > amdgpu_force_vddc) + ps->performance_levels[i].vddc = amdgpu_force_vddc; + } + if (amdgpu_force_vddci) { + if (ps->performance_levels[i].vddci > amdgpu_force_vddci) + ps->performance_levels[i].vddci = amdgpu_force_vddci; + } + if (max_sclk_vddc) { if (ps->performance_levels[i].sclk > max_sclk_vddc) ps->performance_levels[i].sclk = max_sclk_vddc; -- 2.36.1